US12575147USUSPTO Grant XML

3D-stacked transistor structure with barrier layer between upper gate structure and lower gate structure

Provided is a three-dimensionally-stacked field-effect transistor (3DSFET) device including a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET includes: a 1 st channel structure surrounded by a 1 st gate structure; and a 2 nd channel structure surrounded by a 2 nd gate structure, the 2 nd channel structure provided on the 1 st channel structure, and wherein, in at least one of the 3DSFETs, the 1 st gate structure is isolated from the 2 nd gate structure through a barrier layer including a dielectric material comprising tantalum.

Patent

Brief

Patent brief

Problem

How can corrosion in underground pipelines and conduits be prevented?

Novelty

Protective coatings is reinforced by front-page matches on barrier layer.

Uses

Underground pipe, Metal conduit, Industrial line

Assignee

SAMSUNG ELECTRONICS CO., LTD.

Published

Mar 10, 2026

Inventors

Jaejik Baek, Seungchan Yun, Kang-ill Seo

Domain

Infrastructure / energy

Plain-English summary

Problem

How can corrosion in underground pipelines and conduits be prevented?

Solution

three-dimensionally-stacked field-effect transistor (3DSFET) device including a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET includes: a 1 st channel structure surrounded by a 1 st gate structure; and a 2 nd channel structure surrounded by a 2 nd gate structure, the 2 nd channel structure provided on the 1 st channel structure, and wherein, in at least one of the 3DSFETs, the 1 st gate structure is isolated from the 2 nd gate structure through a barrier layer including a dielectric material comprising tantalum.

Key novelty

Protective coatings is reinforced by front-page matches on barrier layer.

Applications

Underground pipeMetal conduitIndustrial line

Relevant search intents

barrier layer

Claims preview

1 . A three-dimensionally-stacked field-effect transistor (3DSFET) device comprising a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET comprises: a 1 st channel structure surrounded by a 1 st gate structure; and a 2 nd channel structure surrounded by a 2 nd gate structure, the 2 nd channel structure provided on the 1 st channel structure, wherein the 1 st channel structure is isolated from the 2 nd channel structure by a channel isolation layer, wherein, in at least one of the 3DSFETs, the 1 st gate structure is isolated from the 2 nd gate structure through a barrier layer comprising a dielectric material comprising tantalum, and wherein the 2 nd gate structure extends toward the 1 st gate structure beyond a top surface of the channel isolation layer. 2 . The 3DSFET device of claim 1 , wherein the barrier layer extends conformally on the 1 st gate structure and on a side surface of the channel isolation layer, and wherein the dielectric material comprises tantalum nitride. 3 . The 3DSFET device of claim 1 , wherein each of the 1 st gate structure and the 2 nd gate structure comprises a high-k dielectric layer, a work-function layer, and a gate electrode, and wherein, in at least one of the 3DSFETs, at least one of the 1 st channel structure and the 2 nd channel structure comprises a high-k dielectric material diffused therein.

Linked approaches

Protective coatings

Barrier layers that isolate metal surfaces from corrosive environments.

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